As is known, structures have been incorporated into ICs to make IC devices less sensitive to ESD events. However, as the size of transistors decreases, conventional ESD protection circuits may be less likely to provide sufficient protection. ESD protection circuits may in some instances negatively impact circuit performance. However, some IC devices have enhanced performance at the expense of ESD protection levels.
Accordingly, it would be desirable and useful to provide enhanced ESD protection levels with little to no impact on IC device performance.